Advanced VLSI Design and Testability Issues

Advanced VLSI Design and Testability Issues

Saxena, Sobhit; Tripathi, Suman Lata; Mohapatra, Sushanta Kumar

Taylor & Francis Ltd

04/2022

360

Mole

Inglês

9780367538361

15 a 20 dias

698

Descrição não disponível.
1. Digital Design with Programmable Logic Devices. 2. Review of Digital Electronics Design. 3 Verilog HDL for Digital and Analog Design. 4. Introduction to Hardware Description Languages. 5. Introduction to Hardware Description Languages (HDLs). 6. Emerging Trends in Nanoscale Semiconductor Devices. 7. Design Challenges and Solutions in CMOS-Based FET. 8. Analytical Design of FET-Based Biosensors. 9. Low-Power FET-Based Bio-sensors. 10. Nanowire Array-Based Gate-All-Around MOSFET for Next-Generation Memory Devices. 11. Design of 7T SRAM Cell Using FinFET Technology. 12. Performance Analysis of AlGaN/GaN Heterostructure Field Effect Transistor (HFET). 13. Synthesis of Polymer-Based Composites for Application in Field-Effect Transistors. 14. Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS technology. 15. Macromodeling and Synthesis of Analog Circuits. 16. Performance-Linked Phase-Locked Loop Architectures: Recent Developments. 17. A Review of Analog-to-Digital and Digital-to-Analog Converters for Smart Antenna Application. 18. Active Inductor-Based VCO for Wireless Communication. 19. Fault Simulation Algorithms: Verilog Implementation. 20. Hardware Protection through Logic Obfuscation.
Este título pertence ao(s) assunto(s) indicados(s). Para ver outros títulos clique no assunto desejado.
Metal Oxide Semiconductor Field - Effect Transistor;Power Consumption;very large scale integration design;Verilog Hdl;integrated circuits;FET;Verilog hardware description languages;VCO;silicon-based field-effect transistor designs;Phase Noise;heterostructure field-effect transistor;Pass Transistor Logic;SRAM Cell;System Verilog;Nanowire FET;Field Effect Transistors;Test Bench;Threshold Voltage;Binary Decision Diagram;7T SRAM Cell;Organic Field Effect Transistor;End Endmodule;VHDL;Nonblocking Assignments;Transistors NMOS4;Flash ADC;Fault Free Circuit;Pal;7T SRAM;Mor Method